The present invention relates to a method of forming planar interconnections between metal layers separated by a dielectric layer in a VLSI device.
The standard technique for interconnecting metal layers through an intermediate dielectric known as the "via process" has been to simply etch a hole defined by a layer of photoresist placed over the dielectric. The etch process used has been either the older wet etch process or a dry etch one. In the wet etch process sloped, isotropically etched side walls result while dry etching creates near-vertical oxide steps due to its anistropic etching behaviour. Generally following dry etching and before metal deposition the intermediate dielectric is heated until it reflows to slope the hole sidewall. This sloping helps to minimize thinning of a metal layer deposited over the walls of the hole. The latter metal deposition provides ohmic contact with the underlying metal layer through the etched hole.
While the via process has proven successful for VLSI and early VLSI technology the shrinking gap between contacts required in advanced VLSI technology has revealed major problems with the via process. The standard via process requires leads which are flared around the top of the via. This flaring requirement restricts the metal pitch and requires about 20 to 30% more bar area.
A step coverage problem arises in via interconnections because of the reduced thickness of conductor laid down over the sidewall of the passageway when making the plug or interconnect conducting layer which can cause excessive circuit resistance of the interconnect.
Due to the lack of planarity of the upper metal layer in the region of the interconnect resulting from the via process a via interconnection can not be laid down over another via interconnection or over a contact.
A design limitation occurs when placing via formed interconnects adjacent to one another on adjacent leads. With extremely tight metal pitches, the slopes of the adjacent interconnects tend to run together and cause metal shorts.
Numerous other potential problems occur due to lack of planarity in via formed interconnects when dealing with multilevel metal systems.
It is therefore an object of this invention to provide an improved method of interconnection between metal layers suitable for high density integrated circuits.
It is a further object to provide a method of interconnection which permits planarity of the upper metal layer in the region of the interconnection.
It is another object of this invention to provide a method of interconnecting metal layers which substantially increases the sidewall pitch of the interconnection and therefore permits closer spacing of adjacent interconnections.